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PRELIMINARY TECHNICAL DATA
FEATURES
True rms response Excellent temperature stability Up to 30 dB input dynamic range at 4 GHz 50 input impedance 1.25 V rms, +15 dBm, maximum input Single-supply operation: 2.7 V to 5.5 V Low power: 3 mW at 3 V supply RoHS Compliant
50 MHz to 4 GHz TruPwrTM Detector ADL5501
FUNCTIONAL BLOCK DIAGRAM
ADL5501
RFIN x2 i
INTERNAL FILTER CAPACITOR
VPOS FLTR
TRANSCONDUCTANCE CELLS x2 i
ERROR AMP BUFFER 100 VRMS
APPLICATIONS
Measurement of CDMA, CDMA2000, W-CDMA, and QPSK/QAM-based OFDM, and other complex modulation waveforms RF transmitter or receiver power measurement
BAND-GAP REFERENCE
ENBL COMM
Figure 1.
GENERAL DESCRIPTION
The ADL5501 is a mean-responding power detector for use in high frequency receiver and transmitter signal chains from 50 MHz to 4 GHz. It is easy to apply, requiring only a single supply between 2.7 V and 5.5 V and a power supply decoupling capacitor. The input is internally ac-coupled and has a nominal input impedance of 50 . The output is a linear-responding dc voltage with a conversion gain of 6.6 V/V rms at 900 MHz. The ADL5501 is intended for true power measurement of simple and complex waveforms. The device is particularly useful for measuring high crest factor (high peak-to-rms ratio) signals, such as CDMA, CDMA2000, W-CDMA, and QPSK/QAM-based OFDM waveforms. The on-chip modulation filter provides adequate averaging for most waveforms. The on-chip, 100 series resistance at the output combined with an external shunt capacitor creates a low-pass filter response that reduces the residual ripple in the dc output voltage. For more complex waveforms, an external capacitor at the FLTR pin can be used for supplementary signal demodulation. The ADL5501 offers excellent temperature stability across a 30 dB range and near 0 dB measurement error across temperature over the top portion of the dynamic range. In addition to its temperature stability, the ADL5501 offers low process variations which further reduces calibration complexity. The ADL5501 operates from -40C to +85C and is available in a 6-lead, 2.0 mm x 2.1 mm SC-70 package. It is fabricated on a proprietary high fT silicon bipolar process.
Rev. PrB
05/05/2006 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2006 Analog Devices, Inc. All rights reserved.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
ADL5501 TARGET SPECIFICATIONS
TA = 25C, VS = 3.0 V, CFLTR = Open, COUT = 100 nF, unless otherwise noted. Table 1.
Parameter FREQUENCY RANGE RMS CONVERSION (f = 100 MHz) Input Impedance Input Return Loss Dynamic Range 1 1 dB Error 2 Conversion Gain Output Intercept 3 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Condition (Input RFIN) (Input RFIN to output VRMS)
PRELIMINARY TECHNICAL DATA
Min 50
Typ
Max 4000
Unit MHz ||pF dB dB dB V/V rms V V V dB/C dB/C ||pF dB dB dB V/V rms V V V dB/C dB/C ||pF dB dB dB V/V rms V V V dB/C dB/C
77||4.7 12.5 CW input, -40C < TA < +85C VS = 3 V VS = 5 V VOUT = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C (Input RFIN to output VRMS) TBD 30 7.4 0.03 3.06 0.17 0.0026 -0.0023 40||0.7 16.5 CW input, -40C < TA < +85C VS = 3 V VS = 5 V VOUT = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C (Input RFIN to output VRMS) TBD 26 6.6 0.03 2.69 0.15 0.0039 -0.0046 64||-0.5 13.5 CW input, -40C < TA < +85C VS = 3 V VS = 5 V VOUT = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C TBD 33 5.7 0.02 2.36 0.13 0.0049 -0.0076
TBD TBD
TBD TBD
RMS CONVERSION (f = 900 MHz) Input Impedance Input Return Loss Dynamic Range 1 dB Error Conversion Gain Output Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity
RMS CONVERSION (f = 1900 MHz) Input Impedance Input Return Loss Dynamic Range 1 dB Error Conversion Gain Output Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity
Rev. PrB | Page 2 of 13
PRELIMINARY TECHNICAL DATA
Parameter RMS CONVERSION (f = 2350 MHz) Input Impedance Input Return Loss Dynamic Range 1 dB Error Conversion Gain Output Intercept Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Condition (Input RFIN to output VRMS) Min Typ 83||-0.06 12 CW input, -40C < TA < +85C VS = 3 V VS = 5 V VOUT = (Gain x VIN) + Intercept PIN = +5 dBm, 400 mV rms PIN = -21 dBm, 20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C No signal at RFIN (Pin ENBL) 2.7 VS 5.5 V, -40C < TA < +85C 2.7 V at ENBL, -40C TA +85C 2.7 VS 5.5 V, -40C < TA < +85C CFLTR = COUT = Open, 0 dBm at RFIN CFLTR = 100nF, COUT = Open, 0 dBm at RFIN -40C < TA < +85C No signal at RFIN, ENBL Input HI 5 No signal at RFIN, ENBL Input LO TBD 32 5.1 0.02 2.11 0.12 0.0051 -0.0142 50 1.8 0.2 -0.5 5 TBD 2.7 1.0 <1 5.5 TBD TBD VPOS TBD 0.8 Max
ADL5501
Unit ||pF dB dB dB V/V rms V V V dB/C dB/C mV V A V s s V mA A
OUTPUT OFFSET ENABLE INTERFACE Logic Level to Enable Power, HI Condition Input Current when HI Logic Level to Disable Power, LO Condition Power-Up Response Time 4 POWER SUPPLY Operating Range Quiescent Current Total Supply Current when Disabled
1 2
The available output swing, and hence the dynamic range, is altered by the supply voltage; see TDB. Error referred to best-fit line at 25C 3 Calculated using linear regression. 4 The response time is measured from 10%-90% of settling level; see TDB. 5 Supply current is input level dependant; see TBD.
Rev. PrB | Page 3 of 13
ADL5501 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage VS VRMS RFIN Equivalent Power, re 50 Internal Power Dissipation JA (SC-70) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 0 V, VS 1.25 V rms 15 dBm TBD mW TBDC/W 125C -40C to +85C -65C to +150C
PRELIMINARY TECHNICAL DATA
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrB | Page 4 of 13
PRELIMINARY TECHNICAL DATA PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPOS 1
6
ADL5501
VRMS
ADL5501
FLTR 2 RFIN 3
5 ENBL TOP VIEW (Not to Scale) 4
COMM
Figure 2. 6-Lead SC-70 Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 Mnemonic VPOS FLTR Description Supply Voltage Pin. Operational range 2.7 V to 5.5 V. Modulation Filter Pin. Connection for an External Capacitor to lower the corner frequency of the modulation filter. Capacitor is connected between FLTR and VS. The on-chip filter is approximately TBD pF. For simple waveforms, no further filtering of the demodulated signal is required. Signal Input Pin. Internally ac-coupled after internal termination resistance. Nominal 50 input impedance. Device Ground Pin. Enable Pin. Connect Pin to VS for Normal Operation. Connect pin to ground for disable mode for a supply current less than 1 A. Output Pin. Rail-to-rail voltage output with limited 3 mA current drive capability. The output has an internal 100 series resistance. High resistive loads are recommended to preserve output swing.
3 4 5 6
RFIN COMM ENBL VRMS
Rev. PrB | Page 5 of 13
ADL5501 TYPICAL PERFORMANCE CHARACTERISTICS
PRELIMINARY TECHNICAL DATA
TA = 25C, VS = 5.0 V, CFLTR = Open, COUT = 100 nF, Colors: black = +25C, blue = -40C, red = +85C, unless otherwise noted.
Figure 3. Output vs. Input Level, Frequencies 100 MHz, 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2700 MHz, 3500 MHz, and 3900 MHz, Supply 5.0 V
Figure 6. Linearity Error vs. Input Level, Freq 100 MHz, 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2700 MHz, 3500 MHz, and 3900 MHz, Supply 5.0 V
Figure 4. Output vs. Input Level (Linear Scale), Freq 100 MHz, 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2700 MHz, 3500 MHz, and 3900 MHz, Supply 5.0 V
3.0
Figure 7. Return Loss vs. Frequency
3.0
2.0
+25C -40C +85C
2.0 1.0 0.0 -1.0 -2.0 -3.0
+25C -40C +85C
ERROR (dB)
0.0
-1.0
-2.0
-3.0 -25 -20 -15 -10 -5 0 INPUT (dBm) 5 10 15
ERROR (dB)
1.0
-25
-20
-15
-10 -5 0 INPUT (dBm)
5
10
15
Figure 5. Temperature Drift Distributions for 3 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 100 MHz, Supply 5.0 V
Figure 8. Output Delta from +25C Output Voltage for 3 Devices at -40C and +85C, Frequency 100 MHz, Supply 5.0 V
Rev. PrB | Page 6 of 13
PRELIMINARY TECHNICAL DATA
3.0
ADL5501
3.0
+25C
2.0
-40C +85C
ERROR (dB)
2.0 1.0 0.0 -1.0 -2.0 -3.0
+25C -40C +85C
1.0 ERROR (dB)
0.0
-1.0
-2.0
-3.0 -25 -20 -15 -10 -5 0 INPUT (dBm) 5 10 15
-25
-20
-15
-10 -5 0 INPUT (dBm)
5
10
15
Figure 9. Temperature Drift Distributions for 3 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 900 MHz, Supply 5.0 V
3.0
Figure 12. Output Delta from +25C Output Voltage for 3 Devices at -40C and +85C, Frequency 900 MHz, Supply 5.0 V
3.0
+25C
2.0
-40C +85C
ERROR (dB)
2.0 1.0 0.0 -1.0 -2.0 -3.0
+25C -40C +85C
1.0 ERROR (dB)
0.0
-1.0
-2.0
-3.0 -25 -20 -15 -10 -5 0 INPUT (dBm) 5 10 15
-25
-20
-15
-10 -5 0 INPUT (dBm)
5
10
15
Figure 10. Temperature Drift Distributions for 3 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 1900 MHz, Supply 5.0 V
3.0
Figure 13. Output Delta from +25C Output Voltage for 3 Devices at -40C and +85C, Frequency 1900 MHz, Supply 5.0 V
3.0
+25C
2.0
-40C +85C
ERROR (dB)
2.0 1.0 0.0 -1.0 -2.0 -3.0
+25C -40C +85C
1.0 ERROR (dB)
0.0
-1.0
-2.0
-3.0 -25 -20 -15 -10 -5 0 INPUT (dBm) 5 10 15
-25
-20
-15
-10 -5 0 INPUT (dBm)
5
10
15
Figure 11. Temperature Drift Distributions for 3 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 2350 MHz, Supply 5.0 V
Figure 14. Output Delta from +25C Output Voltage for 3 Devices at -40C and +85C, Frequency 2350 MHz, Supply 5.0 V
Rev. PrB | Page 7 of 13
ADL5501
3.0
PRELIMINARY TECHNICAL DATA
3.0
+25C
2.0
-40C +85C
ERROR (dB)
2.0 1.0 0.0 -1.0 -2.0 -3.0
+25C -40C +85C
1.0 ERROR (dB)
0.0
-1.0
-2.0
-3.0 -25 -20 -15 -10 -5 0 INPUT (dBm) 5 10 15
-25
-20
-15
-10 -5 0 INPUT (dBm)
5
10
15
Figure 15. Temperature Drift Distributions for 3 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 2700 MHz, Supply 5.0 V
3.0
Figure 18. Output Delta from +25C Output Voltage for 3 Devices at -40C and +85C, Frequency 2700 MHz, Supply 5.0 V
3.0
+25C
2.0
-40C +85C
ERROR (dB)
2.0 1.0 0.0 -1.0 -2.0 -3.0
+25C -40C +85C
1.0 ERROR (dB)
0.0
-1.0
-2.0
-3.0 -25 -20 -15 -10 -5 0 INPUT (dBm) 5 10 15
-25
-20
-15
-10 -5 0 INPUT (dBm)
5
10
15
Figure 16. Temperature Drift Distributions for 3 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 3500 MHz, Supply 5.0 V
3.0
Figure 19. Output Delta from +25C Output Voltage for 3 Devices at -40C and +85C, Frequency 3500 MHz, Supply 5.0 V
3.0
+25C
2.0
-40C +85C
ERROR (dB)
2.0 1.0 0.0 -1.0 -2.0 -3.0
+25C -40C +85C
1.0 ERROR (dB)
0.0
-1.0
-2.0
-3.0 -25 -20 -15 -10 -5 0 INPUT (dBm) 5 10 15
-25
-20
-15
-10 -5 0 INPUT (dBm)
5
10
15
Figure 17. Temperature Drift Distributions for 3 Devices at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 3900 MHz, Supply 5.0 V
Figure 20. Output Delta from +25C Output Voltage for 3 Devices at -40C and +85C, Frequency 3900 MHz, Supply 5.0 V
Rev. PrB | Page 8 of 13
PRELIMINARY TECHNICAL DATA
ADL5501
Figure 21. Error from CW Linear Reference vs. Input with Various WCDMA Up Link Waveforms at 1900 MHz, CFLTR = Open, COUT = 100 nF
Figure 22. Error from CW Linear Reference vs. Input with Various CDMA2000 Reverse Link Waveforms at 900 MHz, CFLTR = 1 nF, COUT = 100 nF
Rev. PrB | Page 9 of 13
ADL5501
EVALUATION BOARD
Figure 23 shows the schematic of the ADL5501 evaluation board. The layout and silkscreen of the evaluation board layers are shown in Figure 24 to Figure 27. The board is powered by a single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by 100 pF and 0.1 F capacitors. Table 4 details the various configuration options of the evaluation board. Problems caused by impedance mismatch can arise using the evaluation board to examine the ADL5501 performance. One way to reduce these problems is to put a coaxial 3 dB attenuator on the RFIN SMA connector. Mismatches at the source, cable, and cable interconnection, as well as those occurring on the evaluation board, can cause these problems. A simple (and common) example of such a problem is triple travel due to mismatch at both the source and the evaluation
PRELIMINARY TECHNICAL DATA
board. Here the signal from the source reaches the evaluation board and mismatch causes a reflection. When that reflection reaches the source mismatch, it causes a new reflection, which travels back to the evaluation board, adding to the original signal incident at the board. The resultant voltage varies with both cable length and frequency dependence on the relative phase of the initial and reflected signals. Placing the 3 dB pad at the input of the board improves the match at the board and thus reduces the sensitivity to mismatches at the source. When such precautions are taken, measurements are less sensitive to cable length and other fixture issues. In an actual application when the distance between ADL5501 and source is short and welldefined, this 3 dB attenuator is not needed.
Figure 23. Evaluation Board Schematic
Table 4. Evaluation Board Configuration Options
Component VPOS, GND C1, C2 C3 R2, R3, C4 Description Ground and Supply Vector Pins. Power Supply Decoupling. The nominal supply decoupling of 0.01 F and 100 pF. Filter Capacitor. The internal averaging capacitor can be augmented by placing additional capacitance in C3. Output Filtering. The combination of the internal 100 output resistance and C4 produce a low-pass filter to reduce output ripple. The output can also be scaled down using the resistor divider pads, R3 and R8. In addition, resistors and capacitors can be placed in C4 and R8 to load test VRMS. Device Enable. When the switch is set towards the "SW1" label, the ENBL pin is connected to VPOS and the ADL5501 is in operating mode. In the opposite switch position, the ENBL pin is grounded (through the 49.9 resistor) putting the device in power-down mode. While in this switch position, the ENBL pin can be driven by a signal generator via the SMA labeled ENBL. In this case, R4 serves as a termination resistor for generators requiring a 50 match. Alternate Interface. R6 allows VOUT to be accessible from the edge connector, which is only used for characterization. Default Condition Not Applicable C1 = 0.1 F (Size 0402) C2 = 100 pF (Size 0402) C3 = Open (Size 0402) R2 = Open (Size 0402) R3 = 0 (Size 0402) C4 = 100 nF (Size 0402) R4 = 49.9 (Size 0402) SW1 = towards "SW1" label
R4, SW1
R1, R5
R1 = Open (Size 0402) R5 = Open (Size 0402)
Rev. PrB | Page 10 of 13
PRELIMINARY TECHNICAL DATA
ADL5501
Figure 24. Layout of Component Side
Figure 26. Silkscreen of Component Side
Figure 25. Layout of Circuit Side
Figure 27. Silkscreen of Circuit Side
Rev. PrB | Page 11 of 13
ADL5501 OUTLINE DIMENSIONS
2.20 2.00 1.80
PRELIMINARY TECHNICAL DATA
1.35 1.25 1.15 PIN 1
6 1
5 2
4 3
2.40 2.10 1.80
0.65 BSC 1.30 BSC 1.00 0.90 0.70 1.10 0.80 0.40 0.10 0.46 0.36 0.26
0.10 MAX
0.30 0.15 0.10 COPLANARITY
SEATING PLANE
0.22 0.08
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 28. 6-Lead Thin Shrink Small Outline Transistor Package [SC-70] (KS-6) Dimensions shown in millimeters
ORDERING GUIDE
Model ADL5501AKSZR7 1 ADL5501AKSZ-R21 ADL5501-EVAL
1
Temperature Range -40C to +85C -40C to +85C
Package Description 6-Lead SC-70, 7" Tape and Reel 6-Lead SC-70, 7" Tape and Reel Evaluation Board
Package Outline KS-6 KS-6
Branding Q0Z Q0Z
Ordering Quantity 3,000 250
Z = Pb-free part.
Rev. PrB | Page 12 of 13
PRELIMINARY TECHNICAL DATA NOTES
ADL5501
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR06056-0-5/06(PrB)
Rev. PrB | Page 13 of 13

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